ECE · Amrita Vishwa Vidyapeetham, Bangalore

Chivukula
Vedajnaa Aparna

Aspiring RTL Design Engineer

Electronics & Communication Engineering student with a strong focus on VLSI, FPGA design, embedded systems, and hardware security. Building real systems — from silicon to sensors.

8.94
GPA / 10
7+
Projects
4th
Year B.Tech
2
Internships
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Who I am

About Me

I'm a final year Electronics and Communication Engineering student at Amrita Vishwa Vidyapeetham, Bangalore, with a GPA of 8.94/10. My interest lies in RTL design, FPGA implementation, and building hardware systems that solve real problems.

My work spans the full stack of digital design — from 45nm CMOS transistor-level simulation in Cadence Virtuoso to FPGA-based AES encryption engines, from embedded FreeRTOS multitasking on STM32 Cortex-M4 to chaos-based secure communication circuits.

I have interned at Hindustan Aeronautical Limited (HAL) and VaidSys Technologies, gaining exposure to real-world aviation electronics and VLSI design environments.

Hindustan Aeronautical Limited (HAL)
Intern · June 2025 · 1 month
Hands-on exposure to radar and Air Traffic Control systems — radar working principles, target tracking, aircraft–ground communication, real-time surveillance, handovers, and conflict resolution.
VaidSys Technologies
Remote Intern · VLSI Domain
Designed and optimized a Pipelined MAC unit in Verilog across three implementations — Basic, 3-stage Pipelined, and Clock-Gated — achieving 40% frequency improvement (188 → 263 MHz) and zero dynamic power during idle via glitch-free latch-based ICG clock gating; verified with STA in Xilinx Vivado.
EDA & Simulation Tools
Cadence VirtuosoXilinx Vivado LTspiceMATLAB ProteusKEIL uVision Dsch-2CISCO Packet Tracer VerilatorGTKWave YosysOpenROAD
Languages & HDL
Verilog HDLSystemVerilog CPython (basics)
Certifications
Udemy · Verilog HDL VLSI Hardware Design Udemy · Verilog for FPGA with Xilinx Vivado
What I've Built

Projects

Click any project to explore technical details, results, and interactive visualizations.

Academic Background

Education

2023 – Present
B.Tech in Electronics & Communication Engineering
Amrita Vishwa Vidyapeetham, Bangalore Campus
GPA: 8.92 / 10.0
2023
Class 12th — CBSE Board
Sri Chaitanya Techno College, Bangalore
Score: 90%
2021
Class 10th — CBSE Board
Sri Chaitanya Techno School, Bangalore
Score: 94.6%
Let's Connect

Get in Touch

aparna.v.c.08@gmail.com